KerberosSDR based receiver


Kerberos SDR is quad channel software defined radio receiver developed by othernet, the  rtl-sdr blog and by myself.

More information on the Kerberos SDR can be found at these locations:,

The hardware can be purchased here:

This page introduces the K8 octa-channel data acquisition system built from Kerberos SDRs. This system was prepared to investigate the passive radar capabilities of the KerberosSDR and to utilize the system as a widely accesible research and development platform for various experiments.

The following sections introduce the main capabilities and the architecture of the system. The detailed discussions of its internal operarion is addressed in the documentation of the Data Acquisition (DAQ) firmware.

System Architecture

The DAQ is responsible for the analog signal reception,digitalization and for the transfer of the digitalized data.  From the hardware structure point of view the core components of the DAQ Subsystem are two Kerberos SDRs and an SBC (Single Board Computer). A simplified block diagram of the data flow is illustrated  in Figure 1.

Figure 1: Simplified data flow block diagram of the Kerberos SDR based DAQ Subsystem

Each of the Kerberos SDR receivers contains four coherent RF receiver channels. At each end of the analog signal paths an ADC (Analog-to-Digital Converter) digitalize the signals and forwards the digital data through a USB connection. These data channels are merged into a single USB data lane with the use of a USB HUB. The block diagram of this data flow can be seen in Figure 2. These USB data lanes are then connected to an SBC, which realize the data acquisition.

Figure 2: Internal data paths of the Kerberos SDR

On the SBC side the raw received digital data is packed into data frames and then transferred to the DSP Subsystem for further processing. The data acquisition is a time critical tasks as all the samples have to be handed over from the USB data buffers to prevent data override and hence sample loss. Taking these considerations into acount the computational heavy  processing taks are avoided in the DAQ SBC.

At the same time this SBC is kept as simple as possible to maintain the low cost producibility of the full system. The high-speed Ethernet connection capability also belongs to the requirements of the SBC, as it has to transfer the acquired data in real-time. The following table summarize some typical data-link requirements.


Figure 3: Remotely accessible octa-channel receiver based on Kerberos SDRs

Synchronization Capabilities of the Data Acquisition Firmware

The firmware of the DAQ performs automatic gain, sample delay, amplitude and phase calibration at every system startup. This calibration procedure is controlled by two finite state machines (FSMs). The gain tunig procedure finds the maximum allowable gain values for each of the receiver channels in order to utilize the full dynamic range of the receiver and hence ensure maximum sensitivity. This feature is especially important to the Kerberos SDR since used the RTL2832U chips have only 8 bit ADCs.


Beside the gain tuning the system is able to automatically compensate the time differences of the individual receiver channels on the level of discrete signal samples and on the level of  phase delays. While the sample missmatches can be atributed to the data acquisition, the phase distortions are inherent to the receiver channels. Other than phase difference compensation, coherent receivers has to deal with amplitude distortions as well, since most of the coherent algorithms assumes fully equalized channels.

The sample delay and IQ calibration procedure can be implemented in a number of way. One of the possibilities is to use a dedicated calibration signal, which is available at all the time and has the required parameters to perform proper calibration. To this end, the Kerberos SDR coherent receiver implements a built-in wideband noise source which ouput is equally distributted among the receiver channels. This calibration source is suitable both for sample delay and for IQ calibration. The calibration process itself is implemented by two disjunct FSMs in the firmware.

Once the sample delay and the IQ calibration is performed with the built in noise source, the firmware steps into a calibration tracking mode, where the sample delay and the IQ calibration state is continuously monitored and maintained using the Illuminator of Opportunity (IoO).The actual state of the calibration is signaled in the  metadata of the downloaded IQ  samples (in the header of the IQ data frame). Note that the firmware does not implement fractional sample delay compensation. The intra sample time delays between the coherent channels are compensated with constaant phase shifts only during the IQ calibration.


Experimental measurments made with this system can be identfied in the VEGA database

using the hardware ID and unit ID fields in the metadata which should be the followings:

Hardware ID: 'K4' / 'K8'

Unit ID: 0